Referring to a cross-sectional view of FIG. 1, a flash memory cell 100 of a flash memory device includes a tunnel dielectric structure 102 typically comprised of silicon dioxide (SiO2) or nitrided oxide as known to one of ordinary skill in the art of integrated circuit fabrication. The tunnel dielectric structure 102 is disposed on a P-well 103 formed within a semiconductor substrate 105. In addition, a floating gate structure 104, comprised of a conductive material such as polysilicon for example, is disposed over the tunnel dielectric structure 102.
In addition, a floating dielectric structure 106, typically comprised of silicon dioxide (SiO2), is disposed over the floating gate structure 104. A control gate structure 108, comprised of a conductive material, such as polysilicon for example, is disposed over the dielectric structure 106. The tunnel dielectric structure 102, the floating gate structure 104, the floating dielectric structure 106, and the control gate structure 108 form a gate stack of the flash memory cell 100.
A drain bit line junction 110 is formed toward the left of the gate stack of the flash memory cell 100 within an active device area of the P-well 103 defined by a STI (shallow trench isolation) structure 107. Similarly, a source bit line junction 114 is formed toward the right of the gate stack of the flash memory cell 100 within the active area of the P-well 103. When the P-well 103 is doped with a P-type dopant, the drain and source bit line junctions 110 and 114 are doped with an N-type dopant, such as arsenic (As) or phosphorous (P) for example, for forming an N-channel flash memory cell 100.
Alternatively, the flash memory cell 100 is fabricated without the N-type dopant being implanted for the source side. In that case, the source bit line is formed from the portion of the active device area 103 toward the right of the gate stack.
A drain silicide 112 is formed with the drain junction 110, and a source silicide 115 is formed with the source junction 114, for providing contact to the drain and source bit line junctions 110 and 114. In addition, a gate silicide 116 is formed with the control gate structure 108 for providing contact to the control gate 108 of the flash memory cell 100.
During the program or erase operations of the flash memory cell 100 of FIG. 1, charge carriers are injected into or tunneled out of the floating gate structure 104. Such variation of the amount of charge carriers within the floating gate structure 104 alters the threshold voltage of the flash memory cell 100, as known to one of ordinary skill in the art of flash memory technology.
For example, when electrons are the charge carriers that are injected into the floating gate structure 104, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are tunneled out of the floating gate structure 104, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the flash memory cell 100, as known to one of ordinary skill in the art of electronics.
FIG. 2 illustrates a circuit diagram representation of the flash memory cell 100 of FIG. 1 including a control gate terminal 150 coupled to the gate silicide 116, a drain terminal 152 coupled to the drain silicide 112, a source terminal 154 coupled to the source silicide 115, and a P-well terminal 156 coupled to the P-well 103. FIG. 3 illustrates a flash memory device 200 comprised of an array of flash memory cells, as known to one of ordinary skill in the art of flash memory technology. Referring to FIG. 3, the array of flash memory cells 200 includes rows and columns of flash memory cells with each flash memory cell having similar structure to the flash memory cell 100 of FIGS. 1 and 2. The array of flash memory cells 200 of FIG. 3 is illustrated with two columns and two rows of flash memory cells for simplicity and clarity of illustration. However, a typical array of flash memory cells comprising an electrically erasable and programmable memory device has more numerous rows and columns of flash memory cells.
Further referring to FIG. 3, in the array of flash memory cells 200 comprising a flash memory device, the control gate terminals of all flash memory cells in a row of the array are coupled together to form a respective word line for that row. In FIG. 3, the control gate terminals of all flash memory cells in the first row are coupled together to form a first word line 202, and the control gate terminals of all flash memory cells in the second row are coupled together to form a second word line 204.
In addition, the drain terminals of all flash memory cells in a column are coupled together to form a respective bit line for that column. In FIG. 3, the drain terminals of all flash memory cells in the first column are coupled together to form a first bit line 206, and the drain terminals of all flash memory cells in the second column are coupled together to form a second bit line 208. Further referring to FIG. 3, the source terminal of all flash memory cells of the array 200 are coupled together to a source voltage VSS, and the P-well terminal of all flash memory cells of the array 200 are coupled together to a substrate voltage VSUB during some modes of operation of the flash memory cell. Such a circuit of the array of flash memory cells comprising the flash memory device 200 is known to one of ordinary skill in the art of flash memory technology.
For efficient operation of the flash memory cell 100, the leakage current through the drain bit line junction 110 is desired to be minimized. Thus, during fabrication of the flash memory cell 100, the leakage current through the drain bit line junction 110 is desired to be characterized. Referring to a cross-sectional view of FIG. 4, a test junction 212 is fabrication for such characterizing of the junction leakage current. The test junction 212 is formed from implantation of a core dopant which is also implanted into the active device area 103 in FIG. 1 before formation of the gate stack of the flash memory cell 100.
Referring to FIG. 4, a P-well 214 is formed within the substrate 105, and the core dopant is implanted into the P-well 214. The core dopant is typically a P-type dopant such as boron for example. The P-well and the junction 212 are surrounded by a STI (shallow trench isolation) structure 216.
Furthermore, referring to FIG. 5, for emulating the drain bit line junction 110, a drain side dopant is implanted into the test junction 212. The drain side dopant is typically an N-type dopant and is also implanted to form the drain bit line junction 110 of the flash memory cell 100. The combination of the core dopant and the drain side dopant implanted into the test junction 212 typically results in an overall N-type junction 212, and emulates the drain bit line junction 110 of the flash memory cell 100.
Referring to FIG. 6, during subsequent fabrication processes, which typically includes etching processes, the top corners 218 of the test junction 212 become etched and rounded adjacent the isolation structure 216. Referring to FIG. 7, subsequently, when a silicide 220 is formed with the junction 212, an extended portion 222 of the silicide 220 extends lower into the junction 212 at the corners 218. The extend portion 222 of the silicide 220 may even punch through the depth of the junction 212.
When a voltage bias is applied across the silicide 220 and the P-well 214 for characterizing leakage current, a high level of leakage current flows through the extended portion 222 of the silicide 220 that extends near or even punches through the junction 212. Such leakage current through the extended portion 222 of the silicide 220 taints the measure of leakage current through the interface between the test junction 212 and the P-well 214 (i.e., the bulk component of the leakage current). In this manner, with the test junction 212 and silicide 220 of FIG. 7, the substantially bulk component of the leakage current through the test junction 212 is not accurately characterized.
Thus, a junction test structure that allows the substantially bulk component of the leakage current to be accurately characterized is desired.